- B330, Portland Square, Drake Circus, Plymouth, PL4 8AA
- +44 1752 586339
- vasilios.kelefouras@plymouth.ac.uk
Profiles
Dr Vasilios Kelefouras
Lecturer in Computer Science
School of Engineering, Computing and Mathematics (Faculty of Science and Engineering)
Biography
Biography
Dr Vasilios Kelefouras joined the Department of Computing at the University of Plymouth in Sept. 2018. His research expertise lies in the field of High Performance Computing, code optimization, optimizing compilers, task scheduling and embedded systems.
He received his Master diploma “Integrated Software and Hardware Systems” of Computer Engineering and Informatics Department of University of Patras in 2008; he graduated with distinction and he earned the 1st Fellowship award. In 2013, he received his PhD from the department of Electrical and Computer Engineering at University of Patras; he composed and won the Greek PhD Research Scholarship.
From September 2013 until December 2016 he had been working as a postdoctoral researcher at VLSI lab at Dept. of Electrical and Computer Engineering, University of Patras. Additionally, from October 2015 until December 2016, he had been working as a postdoctoral researcher at Embedded System Design and Application Lab of Technological Educational Institute of Western Greece. From Jan. 2017 until Dec. 2017 he was a Research Fellow at Distributed Systems and Services Research Group, School of Computing, University of Leeds (UK). Last, from Dec. 2017 until Sept. 2018 he had been working as a Lecturer at Sheffield Hallam University.
Teaching
Teaching
Teaching interests
I am the module leader of
- Parallel Computing (COMP3001)
- Computer Systems (COMP1001)
In the past I have also taught :
- Embedded Programming and the Internet of Things (SOFT261)
- Computer Systems and Networks (NET112)
- Computer Architecture and Low Level Programming (SEC204)
- Computational Problem Solving and Computer Systems (ISAD515)
Research
Research
Research interests
My research area lies in the field of High Performance Computing, code optimization, optimizing compilers, task scheduling and embedded systems.
In the last 11 years I have carried out high-quality research in several European and Greek research projects and published more than 30 research papers in high quality journals and conferences, such as IEEE/ACM transactions and HiPEAC.
I have gained strong R&D experience in optimising software (SW) applications, in terms of execution time, energy consumption and memory size, in a wide range of different hardware (HW) platforms, i.e., single/multi-core CPUs, microcontrollers, hard/soft processors on FPGAs, GPGPUs, clusters; moreover, I have some experience in developing optimized HW-SW co-design solutions and high throughput/low area HW solutions on FPGAs.
Research degrees awarded to supervised students
PhD Projects:
- Improving the performance of HiRep Lattice Simulations software by exploiting the CPU/GPU hardware architecture details and algorithm characteristics (main supervisor)
- Accelerating Machine Learning Algorithms on Heterogeneous Multi-GPU Clusters (co-supervisor)
- Optimising Information Storage for Network Performance Analysis (co-supervisor)
Publications
Publications
Key publications
Key publications are highlighted
Journals
Articles
(2020) 'Illegal Logging Detection Based on Acoustic Surveillance of Forest' Applied Sciences 10, (20) 7379-7379 Publisher Site , DOI Open access
(2019) 'A methodology correlating code optimizations with data memory accesses, execution time and energy consumption' Journal of Supercomputing , DOI Open access
(2018) 'Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management' ACM Transactions on Embedded Computing Systems 17, (3) 1-25 , DOI Open access
(2017) 'A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details' Computing 99, (9) 865-888 , DOI Open access
(2016) 'Array Size Computation under Uniform Overlapping and Irregular Accesses' ACM Transactions on Design Automation of Electronic Systems 21, (2) 1-35 , DOI
(2016) 'A high-performance matrix–matrix multiplication methodology for CPU and GPU architectures' The Journal of Supercomputing 72, (3) 804-844 , DOI
(2015) 'Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs' Journal of Circuits, Systems, and Computers 25, (04) 1650032-1650032 , DOI Open access
(2015) 'A methodology for speeding up loop kernels by exploiting the software information and the memory architecture' Computer Languages, Systems & Structures 41, 21-41 , DOI
(2015) 'A methodology for speeding up matrix vector multiplication for single/multi-core architectures' The Journal of Supercomputing 71, (7) 2644-2667 , DOI
(2014) 'A scalable and near-optimal representation of access schemes for memory management' ACM Transactions on Architecture and Code Optimization 11, (1) 1-25 , DOI
(2014) 'A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD' The Journal of Supercomputing 68, (3) 1418-1440 , DOI
(2013) 'A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization' The Journal of Supercomputing 68, (1) 459-487 , DOI
(2013) 'Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes' ACM Transactions on Design Automation of Electronic Systems 19, (1) 1-30 , DOI
(2013) 'A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices' Journal of Signal Processing Systems 77, (3) 241-255 , DOI
(2013) 'Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints' ACM Transactions on Architecture and Code Optimization 10, (2) 1-25 , DOI
(2013) 'A systematic approach to classify design-time global scheduling techniques' ACM Computing Surveys 45, (2) 1-30 , DOI
(2012) 'On the exploitation of a high-throughput SHA-256 FPGA design for HMAC' ACM Transactions on Reconfigurable Technology and Systems 5, (1) 1-28 , DOI
(2011) 'A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization' IEEE Transactions on Signal Processing 59, (12) 6217-6226 , DOI
(2010) 'A data locality methodology for matrix–matrix multiplication algorithm' The Journal of Supercomputing 59, (2) 830-851 , DOI
Chapters
B1. K. Djemame, R. Kavanagh, V. Kelefouras, A. Aguila, J. Ejarque, R.M. Badia, D. Garcia Perez, C. Pezuela, J-C. Deprez, L. Guedria, R. De Landtsheer and Y. Georgiou, “Towards an Energy-aware Framework for application development and execution in Heterogeneous parallel architectures” In: Accelerators for energy efficient data centers, C. Kachris (Ed.), 2018, pp. 175-196.
B2. H.E. Michail, A.Gregoriades, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Authentication with RIPEMD-160 and other alternatives: A Hardware Design Perspective”, accepted for publishing in the book "Advanced Technologies", ISBN 978-953-7619-X-X, 2010
(2018) 'Towards an Energy-Aware Framework for Application Development and Execution in Heterogeneous Parallel Architectures' Hardware Accelerators in Data Centers Springer
Conference Papers
C6. B A.Emeretlis, V. Kelefouras, G. Theodoridis, , M. Nanou, C.(T.) Politi, K. Georgoulakis, and G.O. Glentis, “FPGA IMPLEMENTATION OF A MIMO DFE IN 40 GB/S DQPSK OPTICAL LINKS”, EUSIPCO 2015, NICE, FRANCE.
C4. Andreas Emeretlis, V. I. Kelefouras, George Theodoridis, George - Othon Glentis, “EFFICIENT FPGA IMPLEMENTATIONS OF VOLTERRA DFES FOR OPTICAL SYSTEMS”, 2014 IEEE Dallas Circuits and Systems Conference (DCAS), Oct 12-13, 2014
C3. Kritikakou, F.Catthoor, G.S. Athanasiou, V.I. Kelefouras and C. Goutis, “A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design”, Proc. Int’l Conf. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 16-19 July 2012
C2. H.E. Michail, V.I. Kelefouras, D. Panagianopoulou, A. Gregoriades, A. Kotsiolis, C.E. Goutis, “HW/SW co-Design Integrating High – Speed Authentication Module for IPSec/IPv6”, Oral Presentation in the fifth International Conference on Digital Telecommunications (ICDT 2010), Athens/Glyfada Greece, 13-19 June 2010
C13. Vasilios Kelefouras, Karim Djemame, Georgios Keramidas, Nikolaos Voros. An analytical model for loop tiling transformation. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI), July 5-7, 2021
C12. J. Becker, L. Masing, T. Dörr, F. Schade, G. Keramidas, C. Antonopoulos, M. Mavropoulos, E. Tiganourias, V. Kelefouras, K. Antonopoulos, N. Voros, U. Durak, A. Ahlbrecht, W. Zaeske, C. Panagiotou, D. Karadimas, N. Adler, A. Sailer, R. Weber, T. Wilhelm, F. Oszwald, D. Reinhardt, M. Chamas, A. Bekan, G. Smethurst, F. Siddiqui, R. Khan, V. Garousi, S. Sezer, V. Morales. XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time
Embedded Software Systems. Accepted for Publication in International Conference on Field-Programmable Logic and Applications (FPL), 2021.
C11. Efstratios Tiganourias, Michail Mavropoulos, Georgios Keramidas, Vasilios Kelefouras, Christos P. Antonopoulos, and Nikolaos Voros. A Hierarchical Profiler of Intermediate Representation Code based on LLVM. Proc. of Mediterranean Conference on Embedded Computing (MECO), 2021
C10. Muna Al-Saadi, Asiya Khan, Vasilios Kelefouras, David J. Walker and Bushra Al-Saadi, Unsupervised Machine Learning-based Elephant and Mice Flow Identification, at Computing Conference 2021, 15-16 July 2021
C9. V.I. Kelefouras, Karim Djemame “Workflow Simulation Aware and Multi-Threading Effective Task Scheduling for Heterogeneous Computing”, 25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC 18) C8. V.I. Kelefouras, K. Djemame “A methodology for efficient code optimizations and memory management”, ACM International Conference on Computing Frontiers 2018 (CF '18), Ischia, Italy
C7. V.I. Kelefouras, Keramidas Georgios, Voros Nikolaos “Cache partitioning + loop tiling: A methodology for effective shared cache management”, IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany
C5. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Representation of Access Schemes for Memory Management», Presentation at the Conference of European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), Amsterdam, The Netherlands, Jan., 2015
C1. H.E. Michail, D.A. Apostolopoulou, L.A. Anastasiou, V.K. Porpodas, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Novel Hardware Implementation of the Cipher Message Authentication Code (CMAC)”, Oral Presentation in 1st Panhellenic Conference on Electronics and Telecommunications (PACET '08), Patras, Greece, 20-22 March
(2018) 'Workflow Simulation Aware and Multi-Threading Effective Task Scheduling for Heterogeneous Computing' 25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) Bengaluru, India 2-/-1/20182-/-1/2018, DOI Open access
(2018) 'A methodology for efficient code optimizations and memory management' ACM International Conference on Computing Frontiers 2018 (CF '18) Ischia, Italy , DOI Open access
(2017) 'Cache partitioning + loop tiling: A methodology for effective shared cache management”' IEEE Computer Society Annual Symposium on VLSI Bochum, Germany 7-/-0/20177-/-0/2017, DOI Open access
(2015) 'FPGA IMPLEMENTATION OF A MIMO DFE IN 40 GB/S DQPSK OPTICAL LINKS' EUSIPCO NICE, FRANCE
(2015) 'Near-optimal & Scalable Representation of Access Schemes for Memory Management' European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) Amsterdam, The Netherlands
(2014) 'EFFICIENT FPGA IMPLEMENTATIONS OF VOLTERRA DFES FOR OPTICAL SYSTEMS' IEEE Dallas Circuits and Systems Conference (DCAS) 0-/-1/20140-/-1/2015
(2012) 'A template-based methodology for efficient microprocessor and FPGA accelerator co-design' 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII) 7-/-0/20127-/-0/2012IEEE , DOI
(2010) 'HW/SW co-Design Integrating High – Speed Authentication Module for IPSec/IPv6' Oral Presentation in the fifth International Conference on Digital Telecommunications (ICDT 2010) Athens/Glyfada Greece
(2009) 'Novel Hardware Implementation of the Cipher Message Authentication Code (CMAC)' Oral Presentation in 1st Panhellenic Conference on Electronics and Telecommunications (PACET '08) Patras Greece