Dr Vasilios Kelefouras
Profiles

Dr Vasilios Kelefouras

Lecturer in Computer Science

School of Computing, Electronics and Mathematics (Faculty of Science and Engineering)

Role

   Dr Vasilios Kelefouras joined the Department of Computing at University of Plymouth in Sept. 2018. His research expertise lies in the field of optimizing compilers, code optimization, High Performance Computing, data transfer optimization, static task scheduling and embedded systems.
  He received his Master diploma “Integrated Software and Hardware Systems” of Computer Engineering and Informatics Department of University of Patras in 2008; he graduated with distinction and he earned the 1st Fellowship award. In 2013, he received his PhD from the department of Electrical and Computer Engineering at University of Patras; he composed and won the Greek PhD Research Scholarship. From Sept. 2013 until Dec 2016 he had been working as a postdoctoral researcher at VLSI lab at Dept. of Electrical and Computer Engineering, University of Patras. Additionally, from Oct. 2015 until Dec. 2016, he had been working as a postdoctoral researcher at Embedded System Design and Application Lab of Technological Educational Institute of Western Greece. From Jan. 2017 until Dec. 2017 he was a Research Fellow at Distributed Systems and Services Research Group, School of Computing, University of Leeds (UK). Last, from Dec. 2017 until Sept. 2018 he had been working as a Lecturer at Sheffield Hallam University.

Teaching interests

I am the module leader of

  • Embedded Programming and the Internet of Things (SOFT261)
  • Computer Systems and Networks (NET112)
  • Computer Science Workshop (AINT514)

Research interests

  My research area lies in the field of optimizing compilers, loop transformations, High Performance Computing, static task scheduling and embedded systems. 
  The last 11 years I have carried out high quality research in several European and Greek research projects and published 28 research papers in high quality journals and conferences, such as IEEE/ACM transactions and HiPEAC. I have gained strong R&D experience in optimizing software (SW) applications, in terms of execution time, energy consumption and memory size, in a wide range of different hardware (HW) platforms, i.e., single/multi-core CPUs, microcontrollers, hard/soft processors on FPGAs, GPGPUs, clusters; moreover, I have some experience in developing optimized HW-SW co-design solutions and high throughput / low area HW solutions on FPGAs.

Publications in international Journals

2019

J18. Vasilios Kelefouras, Karim Djemame, "A methodology correlating code optimizations with data memory accesses, execution time and energy consumption", accepted for publication in journal of Supercomputing (Springer) (IF: 1.532)

2018

J17. V.I. Kelefouras, Keramidas Georgios, Voros Nikolaos, "Combining software cache partitioning and loop tiling for effective shared cache management", ACM Transactions on Embedded Computing Systems (TECS) (IF: 1.367)

2017

J16. V.I. Kelefouras, “A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details", Journal of Computing, Springer (IF: 0.872)

2016

J15. V.I. Kelefouras, A. Kritikakou, I. Mporas and V. Kolonias, “A high performance Matrix-Matrix Multiplication methodology for CPU and GPU architectures”, Journal of Supercomputing, Springer (IF: 1.088)

J14. A.Kritikakou, F. Catthoor, V. Kelefouras and C. Goutis, “Array Size Computation under Uniform Overlapping & Irregular Accesses” ACM Transactions on Design Automation of Electronic Systems (TODAES) (IF: 0.52)

2015

J 13. V.I. Kelefouras, Elissavet Papadima, A. S. Kritikakou and C.E. Goutis, «A Matrix Vector Multiplication Methodology for single/multi-core architectures», Journal of Supercomputing, Springer (IF: 1.088)

J12. V.I. Kelefouras, A.Kritikakou and C. Goutis, « A methodology of speeding up loop kernels by exploiting the software information and the memory architecture», Journal of Computer Languages, Systems & Structures (COMLAN), Elsevier, 2015 (IF: 0.458)

J11. H.E. Michail, G.S. Athanasiou, V.I. Kelefouras, G. Theodoridis, T. Stouraitis, C.E. Goutis, “Area-Throughput trade-offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs” Journal of Circuits, Systems, and Computers (IF: 0.25)

2014

J10. V.I. Kelefouras, A. Kritikakou and C. Goutis «A Matrix Matrix Multiplication Methodology for Single/Multi-core architectures using SIMD», Journal of Supercomputing, Springer, Vol. 68, No. 3, pp. 1418-1440, Jan., 2014 (IF: 0.917)

J9. V.I. Kelefouras, A. Kritikakou and C. Goutis «A Methodology for Speeding Up Edge and Line Detection Algorithms focusing on Memory Architecture Utilization», Journal of Supercomputing, Springer, Vol. 68, No. 1, pp. 459-487, 2014, DOI:10.1007/s11227-013-1049-x, (IF: 0.917)

J8. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «A scalable and near-optimal representation of access schemes for memory management», ACM Transactions on Architecture and code Optimization (TACO), Vol. 11, No.1, Feb., 2014 (IF: 0.824)

2013

J7. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Intra-signal In-place for Non-overlapping & Irregular Access Schemes», ACM Transactions on Design Automation of Electronic Systems, Vol.19, no. 1, Dec., 2013, DOI:10.1145/2534383 (IF: 0.685)

J6. V.I. Kelefouras, A.Kritikakou, Konstantinos Siourounis and C. Goutis, “A methodology for speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices”, Journal of Signal Processing Systems, Springer, Vol. 77, No. 3, pp. 1-15 , 2013, DOI:10.1007/s11265-013-0812-9 (IF: 0.551)

J5. A.Kritikakou, F. Catthoor, G.S. Athanasiou, V.I. Kelefouras and C. Goutis, “Near-optimal Microprocessor & Accelerators Co-Design with Latency & Throughput Constraints”, ACM Transactions on Architecture and Code Optimization (TACO), May, Vol. 10, No. 2, 2013, DOI:10.1145/2459316.2459317 (IF: 0.824)

J4. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, “A systematic approach to classify design-time global scheduling techniques”, Journal of ACM Computed Surveys, Vol. 45, No. 2, Feb. 2013, DOI: 10.1145/2431211.2431213 (IF: 9.169)

2012

J3. N. Alachiotis, V.I. Kelefouras, G. Athanasiou, H. Michail, A. Kritikakou and C. Goutis, “A Data Locality Methodology for Matrix-Matrix Multiplication Algorithm”, Journal of Supercomputing, Springer, 2012, Vol. 59, No. 2, pp. 830--851, DOI: 10.1007/s11227-010-0474-3 (IF:0.917)

J2. H.E. Michail, G.S. Athanasiou, V.I. Kelefouras, G. Theodoridis, C.E. Goutis, “On the exploitation of a high-throughput SHA-256 FPGA design for HMAC”, accepted for publishing in journal of ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 5, Iss. 1, March 2012.

2011
J1. V.I. Kelefouras, G.S. Athanasiou, N. Alachiotis, H. E. Michail, A. S. Kritikakou and C.E. Goutis, “A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization”, IEEE Transactions on Signal Processing, 2011, Vol.59, No 12, pp.6217-6226, DOI:10.1109/TSP.2011.2168525 (IF:2.829)



Publications in international Conferences

2018

C9. V.I. Kelefouras, Karim Djemame “Workflow Simulation Aware and Multi-Threading Effective Task Scheduling for Heterogeneous Computing”, 25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC 18)

C8. V.I. Kelefouras, K. Djemame “A methodology for efficient code optimizations and memory management”, ACM International Conference on Computing Frontiers 2018 (CF '18), Ischia, Italy 

2017

C7. V.I. Kelefouras, Keramidas Georgios, Voros Nikolaos “Cache partitioning + loop tiling: A methodology for effective shared cache management”, IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany

2015

C6. B A.Emeretlis, V. Kelefouras, G. Theodoridis, , M. Nanou, C.(T.) Politi, K. Georgoulakis, and G.O. Glentis, “FPGA IMPLEMENTATION OF A MIMO DFE IN 40 GB/S DQPSK OPTICAL LINKS”, EUSIPCO 2015, NICE, FRANCE.

C5. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Representation of Access Schemes for Memory Management», Presentation at the Conference of European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), Amsterdam, The Netherlands, Jan., 2015

2014

C4. Andreas Emeretlis, V. I. Kelefouras, George Theodoridis, George - Othon Glentis, “EFFICIENT FPGA IMPLEMENTATIONS OF VOLTERRA DFES FOR OPTICAL SYSTEMS”, 2014 IEEE Dallas Circuits and Systems Conference (DCAS), Oct 12-13, 2014

2012

C3. Kritikakou, F.Catthoor, G.S. Athanasiou, V.I. Kelefouras and C. Goutis, “A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design”, Proc. Int’l Conf. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 16-19 July 2012

2010

C2. H.E. Michail, V.I. Kelefouras, D. Panagianopoulou, A. Gregoriades, A. Kotsiolis, C.E. Goutis, “HW/SW co-Design Integrating High – Speed Authentication Module for IPSec/IPv6”, Oral Presentation in the fifth International Conference on Digital Telecommunications (ICDT 2010), Athens/Glyfada Greece, 13-19 June 2010 

C1.  H.E. Michail, D.A. Apostolopoulou, L.A. Anastasiou, V.K. Porpodas, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Novel Hardware Implementation of the Cipher Message Authentication Code (CMAC)”, Oral Presentation in 1st Panhellenic Conference on Electronics and Telecommunications (PACET '08), Patras, Greece, 20-22 March



Book Chapters

B1. K. Djemame, R. Kavanagh, V. Kelefouras, A. Aguila, J. Ejarque, R.M. Badia, D. Garcia Perez, C. Pezuela, J-C. Deprez, L. Guedria, R. De Landtsheer and Y. Georgiou, “Towards an Energy-aware Framework for application development and execution in Heterogeneous parallel architectures” In: Accelerators for energy efficient data centers, C. Kachris (Ed.), 2018, pp. 175-196.

B2. H.E. Michail, A.Gregoriades, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Authentication with RIPEMD-160 and other alternatives: A Hardware Design Perspective”, accepted for publishing in the book "Advanced Technologies", ISBN 978-953-7619-X-X, 2010 


Key publications are highlighted

Journals
Articles
Kelefouras V & Djemame K 2019 'A methodology correlating code optimizations with data memory accesses, execution time and energy consumption' Journal of Supercomputing PEARL
Vasilios K, Georgios K & Nikolaos V 2018 'Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management' ACM Transactions on Embedded Computing Systems 17, (3) 1-25 , DOI PEARL
Kelefouras V 2017 'A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details' Computing 99, (9) 865-888 , DOI PEARL
Kritikakou A, Catthoor F, Kelefouras V & Goutis C 2016 'Array Size Computation under Uniform Overlapping and Irregular Accesses' ACM Transactions on Design Automation of Electronic Systems 21, (2) 1-35 , DOI
Kelefouras V, Kritikakou A, Mporas I & Kolonias V 2016 'A high-performance matrix–matrix multiplication methodology for CPU and GPU architectures' The Journal of Supercomputing 72, (3) 804-844 , DOI
Michail HE, Athanasiou GS, Kelefouras VI, Theodoridis G, Stouraitis T & Goutis CE 2015 'Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs' Journal of Circuits, Systems, and Computers 25, (04) 1650032-1650032 , DOI PEARL
Kelefouras V, Kritikakou A & Goutis C 2015 'A methodology for speeding up loop kernels by exploiting the software information and the memory architecture' Computer Languages, Systems & Structures 41, 21-41 , DOI
Kelefouras V, Kritikakou A, Papadima E & Goutis C 2015 'A methodology for speeding up matrix vector multiplication for single/multi-core architectures' The Journal of Supercomputing 71, (7) 2644-2667 , DOI
Kritikakou A, Catthoor F, Kelefouras V & Goutis C 2014 'A scalable and near-optimal representation of access schemes for memory management' ACM Transactions on Architecture and Code Optimization 11, (1) 1-25 , DOI
Kelefouras V, Kritikakou A & Goutis C 2014 'A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD' The Journal of Supercomputing 68, (3) 1418-1440 , DOI
Kelefouras V, Kritikakou A & Goutis C 2013 'A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization' The Journal of Supercomputing 68, (1) 459-487 , DOI
Kritikakou A, Catthoor F, Kelefouras V & Goutis C 2013 'Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes' ACM Transactions on Design Automation of Electronic Systems 19, (1) 1-30 , DOI
Kelefouras VI, Kritikakou AS, Siourounis K & Goutis CE 2013 'A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices' Journal of Signal Processing Systems 77, (3) 241-255 , DOI
Kritikakou A, Catthoor F, Athanasiou GS, Kelefouras V & Goutis C 2013 'Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints' ACM Transactions on Architecture and Code Optimization 10, (2) 1-25 , DOI
Kritikakou A, Catthoor F, Kelefouras V & Goutis C 2013 'A systematic approach to classify design-time global scheduling techniques' ACM Computing Surveys 45, (2) 1-30 , DOI
Michail HE, Athanasiou GS, Kelefouras V, Theodoridis G & Goutis CE 2012 'On the exploitation of a high-throughput SHA-256 FPGA design for HMAC' ACM Transactions on Reconfigurable Technology and Systems 5, (1) 1-28 , DOI
Kelefouras VI, Athanasiou GS, Alachiotis N, Michail HE, Kritikakou AS & Goutis CE 2011 'A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization' IEEE Transactions on Signal Processing 59, (12) 6217-6226 , DOI
Alachiotis N, Kelefouras VI, Athanasiou GS, Michail HE, Kritikakou AS & Goutis CE 2010 'A data locality methodology for matrix–matrix multiplication algorithm' The Journal of Supercomputing 59, (2) 830-851 , DOI
Chapters
Djemame K, Kavanagh R, Kelefouras V, Aguilà A, Ejarque J, Badia R, Pérez DG, Pezuela C, Deprez J-C, et. al 2018 'Towards an Energy-Aware Framework for Application Development and Execution in Heterogeneous Parallel Architectures' Hardware Accelerators in Data Centers Springer
Conference Papers
Kelefouras V & Djemame K 2018 'Workflow Simulation Aware and Multi-Threading Effective Task Scheduling for Heterogeneous Computing' 25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) Bengaluru, India 17/12/2018 20/12/2018 , DOI PEARL
Kelefouras V & Djemame K 2018 'A methodology for efficient code optimizations and memory management' ACM International Conference on Computing Frontiers 2018 (CF '18) Ischia, Italy , DOI PEARL
Kelefouras V, Keramidas G & Voros N 2017 'Cache partitioning + loop tiling: A methodology for effective shared cache management”' IEEE Computer Society Annual Symposium on VLSI Bochum, Germany 03/07/2017 05/07/2017 , DOI PEARL
Emertlis A, Kelefouras V, Theodoridis G, Nanou M, Politi C, Georgoulakis K & Glentis O 2015 'FPGA IMPLEMENTATION OF A MIMO DFE IN 40 GB/S DQPSK OPTICAL LINKS' EUSIPCO NICE, FRANCE
Kritikakou A, Catthoor F, Kelefouras V & Goutis C 2015 'Near-optimal & Scalable Representation of Access Schemes for Memory Management' European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) Amsterdam, The Netherlands
Emeretlis A, Kelefouras V, Theodoridis G & Glentis O 2014 'EFFICIENT FPGA IMPLEMENTATIONS OF VOLTERRA DFES FOR OPTICAL SYSTEMS' IEEE Dallas Circuits and Systems Conference (DCAS) 12/10/2014 13/10/2015
Kritikakou A, Catthoor F, Athanasiou GS, Kelefouras V & Goutis C 2012 'A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design' 15-22
Michail H, Kelefouras V, Panagianopoulou D, Gregoriades A, Kotsiolis A & Goutis C 2010 'HW/SW co-Design Integrating High – Speed Authentication Module for IPSec/IPv6' Oral Presentation in the fifth International Conference on Digital Telecommunications (ICDT 2010) Athens/Glyfada Greece
Michail H, Apostolopoulou D, Anastasiou L, Porpodas V, Athanasiou G, Kelefouras V & Goutis C 2009 'Novel Hardware Implementation of the Cipher Message Authentication Code (CMAC)' Oral Presentation in 1st Panhellenic Conference on Electronics and Telecommunications (PACET '08) Patras Greece